1. Field of the Invention
The present invention relates to a method of forming a metal silicide layer, and more particularly, to a method of forming a metal silicide layer totally covering the source/drain region.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate has faced problems such as inferior performances due to boron penetration and unavoidable depletion effect, which increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and lowers a driving force of the devices. Therefore, work function metals are used to replace the conventional poly-silicon gate to be the metal gate that is suitable for the high-k gate dielectric layer.
In conventional arts, after forming the transistor with a metal gate, a wiring system is formed thereon to electrically connect the metal gate and the source/drain regions, thereby providing signal input/output pathways for the transistor. The wiring system includes a plurality of contact plugs. The conventional method of forming contact plugs includes the following steps. An inter-layer dielectric (ILD) layer is formed to cover the transistor and the source/drain region at two sides of the transistor, then, the ILD layer is patterned to form a plurality of contact holes that expose the source/drain region. Subsequently, a metal layer such as a tungsten (W) layer is deposited into the contact holes to form the contact plugs connected to the source/drain region.
When the critical dimension (CD) of the transistor decreases, the space between the transistors decreases as well, and a location shift of the formed contact holes during the contact plug process may occur more easily, therefore, the later formed contact plugs may simultaneously contact the metal gate and the source/drain regions thereby causing short circuits more frequently, which may induce unexpected electrical performances of the transistor. Additionally, as the contact hole shift from its predetermined location or the size of the contact hole decreases with the decreasing critical dimension (CD) of the transistor, the area of the metal salicide layer formed on the source/drain region exposed by the contact hole may decrease as well, therefore, the ohmic contact between the metal salicide layer and the later formed contact plug or the ohmic contact between the metal salicide layer and the source/drain region may not be formed properly, which lowers the performances of the transistor. Consequently, how to improve the manufacturing process of the metal salicide layer between the contact plug and the source/drain region is still an important issue in the field.